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Manual Reference Pages  -  SMP (4)


SMP - description of the FreeBSD Symmetric Multi-Processor kernel


I386 Notes
See Also


.Cd options SMP


The SMP kernel implements symmetric multi-processor support.


Support for multi-processor systems is present for all Tier-1 architectures on
.Fx . Currently, this includes amd64, i386, ia64, and sparc64. Support is enabled using
.Cd options SMP . It is permissible to use the SMP kernel configuration on non-SMP equipped motherboards.


For i386 systems, the SMP kernel supports motherboards that follow the Intel MP specification, version 1.4. In addition to
.Cd options SMP , i386 also requires
.Cd device apic . The mptable(1) command may be used to view the status of multi-processor support.

The number of CPUs detected by the system is available in the read-only sysctl variable hw.ncpu.

.Fx allows specific CPUs on a multi-processor system to be disabled. This can be done using the hint.lapic.X.disabled tunable, where X is the APIC ID of a CPU. Setting this tunable to 1 will result in the corresponding CPU being disabled.

The sched_ule(4) scheduler implements CPU topology detection and adjusts the scheduling algorithms to make better use of modern multi-core CPUs. The sysctl variable kern.sched.topology_spec reflects the detected CPU hardware in a parsable XML format. The top level XML tag is <groups>, which encloses one or more <group> tags containing data about individual CPU groups. A CPU group contains CPUs that are detected to be "close" together, usually by being cores in a single multi-core processor. Attributes available in a <group> tag are "level", corresponding to the nesting level of the CPU group and "cache-level", corresponding to the level of CPU caches shared by the CPUs in the group. The <group> tag contains the <cpu> and <flags> tags. The <cpu> tag describes CPUs in the group. Its attributes are "count", corresponding to the number of CPUs in the group and "mask", corresponding to the integer binary mask in which each bit position set to 1 signifies a CPU belonging to the group. The contents (CDATA) of the <cpu> tag is the comma-delimited list of CPU indexes (derived from the "mask" attribute). The <flags> tag contains special tags (if any) describing the relation of the CPUs in the group. The possible flags are currently "HTT" and "SMT", corresponding to the various implementations of hardware multithreading. An example topology_spec output for a system consisting of two quad-core processors is:

  <group level="1" cache-level="0">
    <cpu count="8" mask="0xff">0, 1, 2, 3, 4, 5, 6, 7</cpu>
      <group level="2" cache-level="0">
        <cpu count="4" mask="0xf">0, 1, 2, 3</cpu>
      <group level="2" cache-level="0">
        <cpu count="4" mask="0xf0">4, 5, 6, 7</cpu>

This information is used internally by the kernel to schedule related tasks on CPUs that are closely grouped together.

.Fx supports hyperthreading on Intel CPU’s on the i386 and AMD64 platforms. Because using logical CPUs can cause performance penalties under certain loads, the logical CPUs can be disabled by setting the machdep.hyperthreading_allowed tunable to zero.


cpuset(1), mptable(1), sched_4bsd(4), sched_ule(4), loader(8), sysctl(8), condvar(9), msleep(9), mtx_pool(9), mutex(9), rwlock(9), sema(9), sx(9)


The SMP kernel’s early history is not (properly) recorded. It was developed in a separate CVS branch until April 26, 1997, at which point it was merged into 3.0-current. By this date 3.0-current had already been merged with Lite2 kernel code.

.Fx 5.0 introduced support for a host of new synchronization primitives, and a move towards fine-grained kernel locking rather than reliance on a Giant kernel lock. The SMPng Project relied heavily on the support of BSDi, who provided reference source code from the fine-grained SMP implementation found in
.Bsx .

.Fx 5.0 also introduced support for SMP on the ia64 and sparc64 architectures.


.An Steve Passe Aq
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