makepp_builtin -- Built in rules for makepp
Makepp may be able to figure out how to compile and link your program even if
you specify no rules at all (or if you don't even have a Makeppfile). After
every Makeppfile is loaded, makepp also loads a set of default rules. (These
rules are special in that they do not override any other rules in the
Makeppfile.) The default rule database is stored in the file
"makepp_builtin_rules.mk" in the makepp distribution or library
directory, so you can always look at that to see exactly what the default
Makepp's builtin rules are almost the same as the rules in GNU make, except that
it has no rules for some of the rare languages that GNU make has rules for.
(This is deliberate; I often ran into trouble with GNU make on several
projects that accidentally reused some of the suffixes that GNU make assigned
to those rare languages.) The rules use the same variables as GNU make, with
some possibly useful additions. Makepp is smarter than GNU make about
inferring which compiler to use, and which other objects and libraries to link
Makepp supplies default values for a number of variables. Most of these are
typically used in rules, and are indeed used in the default rules. Their
values can be overridden by assigning to these variables in your Makeppfile or
on the command line.
These variables are documented in "Predefined Variables" in
makepp_variables. If you have any questions about what any variable evaluates
to, you can always put a line like either of these lines in your Makeppfile:
dummy := $(print $(CC))
&echo -- $(CC) # Must be indented less than previous rule.
which simply prints the value of the "$(CC)" variable when the
Makeppfile is loaded. (Incidentally, this is a useful way to debug any
expression that you're not sure is right.)
In simplified form, here is approximately what the compilation rules look like.
If you change the values of any of the indicated variables, the compilation
command is changed as expected.
# For C programs:
$(CC) $(CFLAGS) $(CPPFLAGS) -c $(input) -o $(output)
# For C++ programs:
%.o: %.cxx # and also %.cc, %.cpp, %.c++, and %.C
$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $(input) -o $(output)
# For Fortran programs:
$(FC) $(FFLAGS) -c $(input) -o $(output)
# Yacc and lex:
$(YACC) $(YFLAGS) $(input)
&mv -f y.tab.c $(output)
$(LEX) $(LFLAGS) -t $(input) -o $(output)
If you're curious about the exact details, you can look in the file
in the makepp distribution.
Makepp also knows how to link programs, too. Makepp attempts to be more clever
than the standard Unix make when it comes to figuring out a link command.
Suppose you are trying to build the target program "xyz". Makepp
will try to build this from "xyz.o", and (unlike the standard Unix
make) it will also attempt to infer whether any other objects or libraries
need to be linked in.
The link rule looks something like this:
xyz: $(infer_objects xyz.o, *.o)
$(infer_linker $(inputs)) $(inputs) $(LDFLAGS) $(LDLIBS) $(LIBS) -o $(output)
"$(infer_objects)" attempts to infer what other ".o" files
need to be linked in based on what ".h" files are included.
The "inferred linker" is a special bit of magic that turns into
"$(CC)" if all the sources are C code, "$(CXX)" if any of
the sources are C++, or "$(F77)" if any of the sources are Fortran.
If you don't like the built-in rules, don't use them. If they don't work for
you, your built is probably sufficiently complicated that you need your own
custom Makeppfile anyway.
To turn off the builtin rules, you can add a line like this to your Makeppfile:
makepp_no_builtin = 1
If you do use them, but not the fairly expensive builtin linker rules, you can
turn those off with:
makepp_no_builtin_linker = 1
For backward compatibility, makepp also turns off its default rules if you
include this line somewhere in your Makeppfile:
You can turn off builtin rules for every Makeppfile in the entire build by
specifying the "--no-builtin-rules" option on the command