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NAME
LIBRARYPerformance Counters Library (libpmc, -lpmc) SYNOPSIS
DESCRIPTIONDMC-620 PMU counters may be configured to count any one of a defined set of hardware events. Arm CoreLink DMC-620 Dynamic Memory Controller performance counters are documented in Revision: r0p0, ARM CoreLink DMC-620 Dynamic Memory Controller Technical Reference Manual, ARM Limited, 2017. PMC CapabilitiesDMC-620 PMU counters support the following capabilities:
Event QualifiersEvent specifiers for these PMCs support the following common qualifiers: Class Name PrefixThese PMCs use a class name prefix of
“ Event SpecifiersThe following PMC events are available: SEE ALSOpmc(3), pmc.atom(3), pmc.core(3), pmc.core2(3), pmc.corei7(3), pmc.corei7uc(3), pmc.iaf(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.soft(3), pmc.tsc(3), pmc.westmere(3), pmc.westmereuc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4) HISTORYThe AUTHORSThe Performance Counters Library (libpmc,
-lpmc) library was written by Joseph Koshy
<jkoshy@FreeBSD.org>.
Oleksandr Rybalko
<ray@FreeBSD.org>.
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