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PMC.SANDYBRIDGE(3) |
FreeBSD Library Functions Manual |
PMC.SANDYBRIDGE(3) |
pmc.sandybridge —
measurement events for Intel Sandy Bridge family CPUs
Performance Counters Library (libpmc, -lpmc)
Intel Sandy Bridge CPUs contain PMCs conforming to the version 3 of the Intel
performance measurement architecture. These CPUs may contain up to three
classes of PMCs:
PMC_CLASS_IAF
- Fixed-function counters that count only one hardware event per
counter.
PMC_CLASS_IAP
- Programmable counters that may be configured to count one of a defined set
of hardware events.
PMC_CLASS_TSC
- These PMCs are documented in
pmc.tsc(3).
The number of PMCs available in each class and their widths need
to be determined at run time by calling
pmc_cpuinfo(3).
Intel Sandy Bridge PMCs are documented in
Volume 3B: System Programming Guide, Part
2, Intel(R) 64 and IA-32 Architectures Software
Developers Manual, Order Number: 253669-039US,
Intel Corporation, May
2011.
These PMCs and their supported events are documented in
pmc.iaf(3).
The programmable PMCs support the following capabilities:
Capability |
Support |
PMC_CAP_CASCADE |
No |
PMC_CAP_EDGE |
Yes |
PMC_CAP_INTERRUPT |
Yes |
PMC_CAP_INVERT |
Yes |
PMC_CAP_READ |
Yes |
PMC_CAP_PRECISE |
No |
PMC_CAP_SYSTEM |
Yes |
PMC_CAP_TAGGING |
No |
PMC_CAP_THRESHOLD |
Yes |
PMC_CAP_USER |
Yes |
PMC_CAP_WRITE |
Yes |
Event specifiers for these PMCs support the following common qualifiers:
rsp= value
- Configure the Off-core Response bits.
REQ_DMND_DATA_RD
- Counts the number of demand and DCU prefetch data reads of full and
partial cachelines as well as demand data page table entry cacheline
reads. Does not count L2 data read prefetches or instruction
fetches.
REQ_DMND_RFO
- Counts the number of demand and DCU prefetch reads for ownership (RFO)
requests generated by a write to data cacheline. Does not count L2 RFO
prefetches.
REQ_DMND_IFETCH
- Counts the number of demand and DCU prefetch instruction cacheline
reads. Does not count L2 code read prefetches.
REQ_WB
- Counts the number of writeback (modified to exclusive)
transactions.
REQ_PF_DATA_RD
- Counts the number of data cacheline reads generated by L2
prefetchers.
REQ_PF_RFO
- Counts the number of RFO requests generated by L2 prefetchers.
REQ_PF_IFETCH
- Counts the number of code reads generated by L2 prefetchers.
REQ_PF_LLC_DATA_RD
- L2 prefetcher to L3 for loads.
REQ_PF_LLC_RFO
- RFO requests generated by L2 prefetcher
REQ_PF_LLC_IFETCH
- L2 prefetcher to L3 for instruction fetches.
REQ_BUS_LOCKS
- Bus lock and split lock requests.
REQ_STRM_ST
- Streaming store requests.
REQ_OTHER
- Any other request that crosses IDI, including I/O.
RES_ANY
- Catch all value for any response types.
RES_SUPPLIER_NO_SUPP
- No Supplier Information available.
RES_SUPPLIER_LLC_HITM
- M-state initial lookup stat in L3.
RES_SUPPLIER_LLC_HITE
- E-state.
RES_SUPPLIER_LLC_HITS
- S-state.
RES_SUPPLIER_LLC_HITF
- F-state.
RES_SUPPLIER_LOCAL
- Local DRAM Controller.
RES_SNOOP_SNP_NONE
- No details on snoop-related information.
RES_SNOOP_SNP_NO_NEEDED
- No snoop was needed to satisfy the request.
RES_SNOOP_SNP_MISS
- A snoop was needed and it missed all snooped caches: -For LLC Hit,
ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by
all sockets and data was returned from DRAM.
RES_SNOOP_HIT_NO_FWD
- A snoop was needed and it hits in at least one snooped cache. Hit
denotes a cache-line was valid before snoop effect. This includes:
-Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC
Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward
(LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from
DRAM.
RES_SNOOP_HIT_FWD
- A snoop was needed and data was forwarded from a remote socket. This
includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss,
IFetch/Data_RD/RFT).
RES_SNOOP_HITM
- A snoop was needed and it HitM-ed in local or remote cache. HitM
denotes a cache-line was in modified state before effect as a results
of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop
MtoS (LLC Hit, IFetch/Data_RD).
RES_NON_DRAM
- Target was non-DRAM system address. This includes MMIO
transactions.
cmask= value
- Configure the PMC to increment only if the number of configured events
measured in a cycle is greater than or equal to
value.
edge
- Configure the PMC to count the number of de-asserted to asserted
transitions of the conditions expressed by the other qualifiers. If
specified, the counter will increment only once whenever a condition
becomes true, irrespective of the number of clocks during which the
condition remains true.
inv
- Invert the sense of comparison when the
“
cmask ” qualifier is present, making
the counter increment when the number of events per cycle is less than the
value specified by the “cmask ”
qualifier.
os
- Configure the PMC to count events happening at processor privilege level
0.
usr
- Configure the PMC to count events occurring at privilege levels 1, 2 or
3.
If neither of the “os ” or
“usr ” qualifiers are specified, the
default is to enable both.
Sandy Bridge programmable PMCs support the following events:
LD_BLOCKS.DATA_UNKNOWN
- (EVENT_03H, Umask 01H) Blocked loads due to store buffer blocks with
unknown data.
LD_BLOCKS.STORE_FORWARD
- (Event 03H, Umask 02H) Loads blocked by overlapping with store buffer that
cannot be forwarded.
LD_BLOCKS.NO_SR
- (Event 03H, Umask 08H) # of Split loads blocked due to resource not
available.
LD_BLOCKS.ALL_BLOCK
- (EVENT_03H, Umask 10H) Number of cases where any load is blocked but has
no DCU miss.
MISALIGN_MEM_REF.LOADS
- (Event 05H, Umask 01H) Speculative cache-line split load uops dispatched
to L1D.
MISALIGN_MEM_REF.STORES
- (Event 05H, Umask 02H) Speculative cache-line split Store-address uops
dispatched to L1D.
LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
- (Event 07H, Umask 01H) False dependencies in MOB due to partial compare on
address.
LD_BLOCKS_PARTIAL.ALL_STA_BLOCK
- (Event 07H, Umask 08H) The number of times that load operations are
temporarily blocked because of older stores, with addresses that are not
yet known. A load operation may incur more than one block of this
type.
- LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
- (Event 08H, Umask 01H) Misses in all TLB levels that cause a page walk of
any page size.
DTLB_LOAD_MISSES.WALK_COMPLETED
- (Event 08H, Umask 02H) Misses in all TLB levels that caused page walk
completed of any size.
DTLB_LOAD_MISSES.WALK_DURATION
- (Event 08H, Umask 04H) Cycle PMH is busy with a walk.
DTLB_LOAD_MISSES.STLB_HIT
- (Event 08H, Umask 10H) Number of cache load STLB hits. No page walk.
INT_MISC.RECOVERY_CYCLES
- (Event 0DH, Umask 03H) Cycles waiting to recover after Machine Clears or
JEClear. Set Cmask = 1. Set Edge to count occurrences
INT_MISC.RAT_STALL_CYCLES
- (Event 0DH, Umask 40H) Cycles RAT external stall is sent to IDQ for this
thread.
UOPS_ISSUED.ANY
- (Event 0EH, Umask 01H) Increments each cycle the # of Uops issued by the
RAT to RS. Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this
core. Set Cmask = 1, Inv = 1 to count stalled cycles
FP_COMP_OPS_EXE.X87
- (Event 10H, Umask 01H) Counts number of X87 uops executed.
FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE
- (Event 10H, Umask 10H) Counts number of SSE* double precision FP packed
uops executed.
FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE
- (Event 10H, Umask 20H) Counts number of SSE* single precision FP scalar
uops executed.
FP_COMP_OPS_EXE.SSE_PACKED_SINGLE
- (Event 10H, Umask 40H) Counts number of SSE* single precision FP packed
uops executed.
- LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE
- (Event 10H, Umask 80H) Counts number of SSE* double precision FP scalar
uops executed.
SIMD_FP_256.PACKED_SINGLE
- (Event 11H, Umask 01H) Counts 256-bit packed single-precision
floating-point instructions.
SIMD_FP_256.PACKED_DOUBLE
- (Event 11H, Umask 02H) Counts 256-bit packed double-precision
floating-point instructions.
ARITH.FPU_DIV_ACTIVE
- (Event 14H, Umask 01H) Cycles that the divider is active, includes INT and
FP. Set 'edge =1, cmask=1' to count the number of divides.
INSTS_WRITTEN_TO_IQ.INSTS
- (Event 17H, Umask 01H) Counts the number of instructions written into the
IQ every cycle.
L2_RQSTS.DEMAND_DATA_RD_HIT
- (Event 24H, Umask 01H) Demand Data Read requests that hit L2 cache.
L2_RQSTS.ALL_DEMAND_DATA_RD
- (Event 24H, Umask 03H) Counts any demand and L1 HW prefetch data load
requests to L2.
L2_RQSTS.RFO_HITS
- (Event 24H, Umask 04H) Counts the number of store RFO requests that hit
the L2 cache.
L2_RQSTS.RFO_MISS
- (Event 24H, Umask 08H) Counts the number of store RFO requests that miss
the L2 cache.
L2_RQSTS.ALL_RFO
- (Event 24H, Umask 0CH) Counts all L2 store RFO requests.
L2_RQSTS.CODE_RD_HIT
- (Event 24H, Umask 10H) Number of instruction fetches that hit the L2
cache.
L2_RQSTS.CODE_RD_MISS
- (Event 24H, Umask 20H) Number of instruction fetches that missed the L2
cache.
L2_RQSTS.ALL_CODE_RD
- (Event 24H, Umask 30H) Counts all L2 code requests.
L2_RQSTS.PF_HIT
- (Event 24H, Umask 40H) Requests from L2 Hardware prefetcher that hit
L2.
L2_RQSTS.PF_MISS
- (Event 24H, Umask 80H) Requests from L2 Hardware prefetcher that missed
L2.
L2_RQSTS.ALL_PF
- (Event 24H, Umask C0H) Any requests from L2 Hardware prefetchers.
L2_STORE_LOCK_RQSTS.MISS
- (Event 27H, Umask 01H) RFOs that miss cache lines.
L2_STORE_LOCK_RQSTS.HIT_E
- (Event 27H, Umask 04H) RFOs that hit cache lines in E state.
L2_STORE_LOCK_RQSTS.HIT_M
- (EVENT_27H, Umask 08H) RFOs that hit cache lines in M state.
L2_STORE_LOCK_RQSTS.ALL
- (EVENT_27H, Umask 0FH) RFOs that access cache lines in any state.
L2_L1D_WB_RQSTS.HIT_E
- (Event 28H, Umask 04H) Not rejected writebacks from L1D to L2 cache lines
in E state.
L2_L1D_WB_RQSTS.HIT_M
- (Event 28H, Umask 08H) Not rejected writebacks from L1D to L2 cache lines
in M state.
LONGEST_LAT_CACHE.REFERENCE
- (Event 2EH, Umask 4FH) This event counts requests originating from the
core that reference a cache line in the last level cache.
LONGEST_LAT_CACHE.MISS
- (Event 2EH, Umask 41H) This event counts each cache miss condition for
references to the last level cache.
CPU_CLK_UNHALTED.THREAD_P
- (Event 3CH, Umask 00H) Counts the number of thread cycles while the thread
is not in a halt state. The thread enters the halt state when it is
running the HLT instruction. The core frequency may change from time to
time due to power or thermal throttling.
CPU_CLK_THREAD_UNHALTED.REF_XCLK
- (Event 3CH, Umask 01H) Increments at the frequency of XCLK (100 MHz) when
not halted.
L1D_PEND_MISS.PENDING
- (Event 48H, Umask 01H) Increments the number of outstanding L1D misses
every cycle. Set Cmask = 1 and Edge =1 to count occurrences. Counter 2
only; Set Cmask = 1 to count cycles.
DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
- (Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any)
page size (4K/2M/4M/1G).
DTLB_STORE_MISSES.WALK_COMPLETED
- (Event 49H, Umask 02H) Miss in all TLB levels causes a page walk that
completes of any page size (4K/2M/4M/1G).
DTLB_STORE_MISSES.WALK_DURATION
- (Event 49H, Umask 04H) Cycles PMH is busy with this walk.
DTLB_STORE_MISSES.STLB_HIT
- (Event 49H, Umask 10H) Store operations that miss the first TLB level but
hit the second and do not cause page walks.
LOAD_HIT_PRE.SW_PF
- (Event 4CH, Umask 01H) Not SW-prefetch load dispatches that hit fill
buffer allocated for S/W prefetch.
LOAD_HIT_PER.HW_PF
- (Event 4CH, Umask 02H) Not SW-prefetch load dispatches that hit fill
buffer allocated for H/W prefetch.
HW_PRE_REQ.DL1_MISS
- (Event 4EH, Umask 02H) Hardware Prefetch requests that miss the L1D cache.
A request is being counted each time it access the cache & miss it,
including if a block is applicable or if hit the Fill Buffer for example.
This accounts for both L1 streamer and IP-based (IPP) HW prefetchers.
L1D.REPLACEMENT
- (Event 51H, Umask 01H) Counts the number of lines brought into the L1 data
cache.
L1D.ALLOCATED_IN_M
- (Event 51H, Umask 02H) Counts the number of allocations of modified L1D
cache lines.
L1D.EVICTION
- (Event 51H, Umask 04H) Counts the number of modified lines evicted from
the L1 data cache due to replacement.
L1D.ALL_M_REPLACEMENT
- (Event 51H, Umask 08H) Cache lines in M state evicted out of L1D due to
Snoop HitM or dirty line replacement.
PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP
- (Event 59H, Umask 20H) Increments the number of flags-merge uops in flight
each cycle. Set Cmask = 1 to count cycles.
PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW
- (Event 59H, Umask 40H) Cycles with at least one slow LEA uop
allocated.
PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
- (Event 59H, Umask 80H) Number of Multiply packed/scalar single precision
uops allocated.
RESOURCE_STALLS2.ALL_FL_EMPTY
- (Event 5BH, Umask 0CH) Cycles stalled due to free list empty.
RESOURCE_STALLS2.ALL_PRF_CONTROL
- (Event 5BH, Umask 0FH) Cycles stalled due to control structures full for
physical registers.
RESOURCE_STALLS2.BOB_FULL
- (Event 5BH, Umask 40H) Cycles Allocator is stalled due to Branch Order
Buffer.
RESOURCE_STALLS2.OOO_RSRC
- (Event 5BH, Umask 4FH) Cycles stalled due to out of order resources
full.
CPL_CYCLES.RING0
- (Event 5CH, Umask 01H) Unhalted core cycles when the thread is in ring 0.
Use Edge to count transition
CPL_CYCLES.RING123
- (Event 5CH, Umask 02H) Unhalted core cycles when the thread is not in ring
0.
RS_EVENTS.EMPTY_CYCLES
- (Event 5EH, Umask 01H) Cycles the RS is empty for the thread.
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
- (Event 60H, Umask 01H) Offcore outstanding Demand Data Read transactions
in SQ to uncore. Set Cmask=1 to count cycles.
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
- (Event 60H, Umask 04H) Offcore outstanding RFO store transactions in SQ to
uncore. Set Cmask=1 to count cycles.
OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
- (Event 60H, Umask 08H) Offcore outstanding cacheable data read
transactions in SQ to uncore. Set Cmask=1 to count cycles.
LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
- (Event 63H, Umask 01H) Cycles in which the L1D and L2 are locked, due to a
UC lock or split lock.
LOCK_CYCLES.CACHE_LOCK_DURATION
- (Event 63H, Umask 02H) Cycles in which the L1D is locked.
IDQ.EMPTY
- (Event 79H, Umask 02H) Counts cycles the IDQ is empty.
IQD.MITE_UOPS
- (Event 79H, Umask 04H) Increment each cycle # of uops delivered to IDQ
from MITE path. Set Cmask = 1 to count cycles. Can combine Umask 04H and
20H
IDQ.DSB_UOPS
- (Event 79H, Umask 08H) Increment each cycle. # of uops delivered to IDQ
from DSB path. Set Cmask = 1 to count cycles. Can combine Umask 08H and
10H
IDQ.MS_DSB_UOPS
- (Event 79H, Umask 10H) Increment each cycle # of uops delivered to IDQ
when MS busy by DSB. Set Cmask = 1 to count cycles MS is busy. Set Cmask=1
and Edge=1 to count MS activations. Can combine Umask 08H and 10H
IDQ.MS_MITE_UOPS
- (Event 79H, Umask 20H) Increment each cycle # of uops delivered to IDQ
when MS is busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask
04H and 20H
IDQ.MS_UOPS
- (Event 79H, Umask 30H) Increment each cycle # of uops delivered to IDQ
from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine
Umask 04H, 08H and 30H
ICACHE.MISSES
- (Event 80H, Umask 02H) Number of Instruction Cache, Streaming Buffer and
Victim Cache Misses. Includes UC accesses.
ITLB_MISSES.MISS_CAUSES_A_WALK
- (Event 85H, Umask 01H) Misses in all ITLB levels that cause page
walks.
ITLB_MISSES.WALK_COMPLETED
- (Event 85H, Umask 02H) Misses in all ITLB levels that cause completed page
walks.
ITLB_MISSES.WALK_DURATION
- (Event 85H, Umask 04H) Cycle PMH is busy with a walk.
ITLB_MISSES.STLB_HIT
- (Event 85H, Umask 10H) Number of cache load STLB hits. No page walk.
ILD_STALL.LCP
- (Event 87H, Umask 01H) Stalls caused by changing prefix length of the
instruction.
ILD_STALL.IQ_FULL
- (Event 87H, Umask 04H) Stall cycles due to IQ is full.
BR_INST_EXEC.NONTAKEN_COND
- (Event 88H, Umask 41H) Count conditional near branch instructions that
were executed (but not necessarily retired) and not taken.
BR_INST_EXEC.TAKEN_COND
- (Event 88H, Umask 81H) Count conditional near branch instructions that
were executed (but not necessarily retired) and taken.
BR_INST_EXEC.DIRECT_JMP
- (Event 88H, Umask 82H) Count all unconditional near branch instructions
excluding calls and indirect branches.
BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
- (Event 88H, Umask 84H) Count executed indirect near branch instructions
that are not calls nor returns.
BR_INST_EXEC.RETURN_NEAR
- (Event 88H, Umask 88H) Count indirect near branches that have a return
mnemonic.
BR_INST_EXEC.DIRECT_NEAR_CALL
- (Event 88H, Umask 90H) Count unconditional near call branch instructions,
excluding non call branch, executed.
BR_INST_EXEC.INDIRECT_NEAR_CALL
- (Event 88H, Umask A0H) Count indirect near calls, including both register
and memory indirect, executed.
BR_INST_EXEC.ALL_BRANCHES
- (Event 88H, Umask FFH) Counts all near executed branches (not necessarily
retired).
BR_MISP_EXEC.NONTAKEN_COND
- (Event 89H, Umask 41H) Count conditional near branch instructions
mispredicted as nontaken.
BR_MISP_EXEC.TAKEN_COND
- (Event 89H, Umask 81H) Count conditional near branch instructions
mispredicted as taken.
BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
- (Event 89H, Umask 84H) Count mispredicted indirect near branch
instructions that are not calls nor returns.
BR_MISP_EXEC.RETURN_NEAR
- (Event 89H, Umask 88H) Count mispredicted indirect near branches that have
a return mnemonic.
BR_MISP_EXEC.DIRECT_NEAR_CALL
- (Event 89H, Umask 90H) Count mispredicted unconditional near call branch
instructions, excluding non call branch, executed.
BR_MISP_EXEC.INDIRECT_NEAR_CALL
- (Event 89H, Umask A0H) Count mispredicted indirect near calls, including
both register and memory indirect, executed.
BR_MISP_EXEC.ALL_BRANCHES
- (Event 89H, Umask FFH) Counts all mispredicted near executed branches (not
necessarily retired).
IDQ_UOPS_NOT_DELIVERED.CORE
- (Event 9CH, Umask 01H) Count number of non-delivered uops to RAT per
thread. Use Cmask to qualify uop b/w
UOPS_DISPATCHED_PORT.PORT_0
- (Event A1H, Umask 01H) Cycles which a Uop is dispatched on port 0.
UOPS_DISPATCHED_PORT.PORT_1
- (Event A1H, Umask 02H) Cycles which a Uop is dispatched on port 1.
UOPS_DISPATCHED_PORT.PORT_2_LD
- (Event A1H, Umask 04H) Cycles which a load uop is dispatched on port
2.
UOPS_DISPATCHED_PORT.PORT_2_STA
- (Event A1H, Umask 08H) Cycles which a store address uop is dispatched on
port 2.
UOPS_DISPATCHED_PORT.PORT_2
- (Event A1H, Umask 0CH) Cycles which a Uop is dispatched on port 2.
UOPS_DISPATCHED_PORT.PORT_3_LD
- (Event A1H, Umask 10H) Cycles which a load uop is dispatched on port
3.
UOPS_DISPATCHED_PORT.PORT_3_STA
- (Event A1H, Umask 20H) Cycles which a store address uop is dispatched on
port 3.
UOPS_DISPATCHED_PORT.PORT_3
- (Event A1H, Umask 30H) (Cycles which a Uop is dispatched on port 3.)
UOPS_DISPATCHED_PORT.PORT_4
- (Event A1H, Umask 40H) Cycles which a Uop is dispatched on port 4.
UOPS_DISPATCHED_PORT.PORT_5
- (Event A1H, Umask 80H) Cycles which a Uop is dispatched on port 5.
RESOURCE_STALLS.ANY
- (Event A2H, Umask 01H) Cycles Allocation is stalled due to Resource
Related reason.
RESOURCE_STALLS.LB
- (Event A2H, Umask 02H) Counts the cycles of stall due to lack of load
buffers.
RESOURCE_STALLS.LB
- (Event A2H, Umask 04H) Cycles stalled due to no eligible RS entry
available.
RESOURCE_STALLS.SB
- (Event A2H, Umask 08H) Cycles stalled due to no store buffers available.
(not including draining form sync)
RESOURCE_STALLS.ROB
- (Event A2H, Umask 10H) Cycles stalled due to re-order buffer full.
RESOURCE_STALLS.FCSW
- (Event A2H, Umask 20H) Cycles stalled due to writing the FPU control
word.
RESOURCE_STALLS.MXCSR
- (Event A2H, Umask 40H) Cycles stalled due to the MXCSR register rename
occurring to close to a previous MXCSR rename.
RESOURCE_STALLS.OTHER
- (Event A2H, Umask 80H) Cycles stalled while execution was stalled due to
other resource issues.
DSB2MITE_SWITCHES.COUNT
- (Event ABH, Umask 01H) Number of DSB to MITE switches.
DSB2MITE_SWITCHES.PENALTY_CYCLES
- (Event ABH, Umask 02H) Cycles DSB to MITE switches caused delay.
DSB_FILL.OTHER_CANCEL
- (Event ACH, Umask 02H) Cases of cancelling valid DSB fill not because of
exceeding way limit.
DSB_FILL.EXCEED_DSB_LINES
- (Event ACH, Umask 08H) DSB Fill encountered > 3 DSB lines.
DSB_FILL.ALL_CANCEL
- (Event ACH, Umask 0AH) Cases of cancelling valid Decode Stream Buffer
(DSB) fill not because of exceeding way limit.
ITLB.ITLB_FLUSH
- (Event AEH, Umask 01H) Counts the number of ITLB flushes, includes
4k/2M/4M pages.
OFFCORE_REQUESTS.DEMAND_DATA_RD
- (Event B0H, Umask 01H) Demand data read requests sent to uncore.
OFFCORE_REQUESTS.DEMAND_RFO
- (Event B0H, Umask 04H) Demand RFO read requests sent to uncore, including
regular RFOs, locks, ItoM.
OFFCORE_REQUESTS.ALL_DATA_RD
- (Event B0H, Umask 08H) Data read requests sent to uncore (demand and
prefetch).
UOPS_DISPATCHED.THREAD
- (Event B1H, Umask 01H) Counts total number of uops to be dispatched
per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.
UOPS_DISPATCHED.CORE
- (Event B1H, Umask 02H) Counts total number of uops to be dispatched
per-core each cycle. Do not need to set ANY
OFFCORE_REQUESTS_BUFFER.SQ_FULL
- (Event B2H, Umask 01H) Offcore requests buffer cannot take more entries
for this thread core.
AGU_BYPASS_CANCEL.COUNT
- (Event B6H, Umask 01H) Counts executed load operations with all the
following traits: 1. addressing of the format [base + offset], 2. the
offset is between 1 and 2047, 3. the address specified in the base
register is in one page and the address [base+offset] is in another
page.
OFF_CORE_RESPONSE_0
- (Event B7H, Umask 01H) Off-core Response Performance Monitoring; PMC0
only. Requires programming MSR 01A6H
OFF_CORE_RESPONSE_1
- (Event BBH, Umask 01H) Off-core Response Performance Monitoring. PMC3
only. Requires programming MSR 01A7H
TLB_FLUSH.DTLB_THREAD
- (Event BDH, Umask 01H) DTLB flush attempts of the thread-specific
entries.
TLB_FLUSH.STLB_ANY
- (Event BDH, Umask 20H) Count number of STLB flush attempts.
L1D_BLOCKS.BANK_CONFLICT_CYCLES
- (Event BFH, Umask 05H) Cycles when dispatched loads are cancelled due to
L1D bank conflicts with other load ports. cmask=1
INST_RETIRED.ANY_P
- (Event C0H, Umask 00H) Number of instructions at retirement.
INST_RETIRED.PREC_DIST
- (Event C0H, Umask 01H) Precise instruction retired event with HW to reduce
effect of PEBS shadow in IP distribution PMC1 only; Must quiesce other
PMCs.
INST_RETIRED.X87
- (Event C0H, Umask 02H) X87 instruction retired event.
OTHER_ASSISTS.ITLB_MISS_RETIRED
- (Event C1H, Umask 02H) Instructions that experienced an ITLB miss.
OTHER_ASSISTS.AVX_STORE
- (Event C1H, Umask 08H) Number of assists associated with 256-bit AVX store
operations.
OTHER_ASSISTS.AVX_TO_SSE
- (Event C1H, Umask 10H) Number of transitions from AVX256 to legacy SSE
when penalty applicable.
OTHER_ASSISTS.SSE_TO_AVX
- (Event C1H, Umask 20H) Number of transitions from SSE to AVX-256 when
penalty applicable.
UOPS_RETIRED.ALL
- (Event C2H, Umask 01H) Counts the number of micro-ops retired. Use cmask=1
and invert to count active cycles or stalled cycles.
UOPS_RETIRED.RETIRE_SLOTS
- (Event C2H, Umask 02H) Counts the number of retirement slots used each
cycle.
MACHINE_CLEARS.MEMORY_ORDERING
- (Event C3H, Umask 02H) Counts the number of machine clears due to memory
order conflicts.
MACHINE_CLEARS.SMC
- (Event C3H, Umask 04H) Counts the number of times that a program writes to
a code section.
MACHINE_CLEARS.MASKMOV
- (Event C3H, Umask 20H) Counts the number of executed AVX masked load
operations that refer to an illegal address range with the mask bits set
to 0.
BR_INST_RETIRED.ALL_BRANCH
- (Event C4H, Umask 00H) Branch instructions at retirement.
BR_INST_RETIRED.CONDITIONAL
- (Event C4H, Umask 01H) Counts the number of conditional branch
instructions retired.
BR_INST_RETIRED.NEAR_CALL
- (Event C4H, Umask 02H) Direct and indirect near call instructions
retired.
BR_INST_RETIRED.ALL_BRANCHES
- (Event C4H, Umask 04H) Counts the number of branch instructions
retired.
BR_INST_RETIRED.NEAR_RETURN
- (Event C4H, Umask 08H) Counts the number of near return instructions
retired.
BR_INST_RETIRED.NOT_TAKEN
- (Event C4H, Umask 10H) Counts the number of not taken branch instructions
retired.
BR_INST_RETIRED.NEAR_TAKEN
- (Event C4H, Umask 20H) Number of near taken branches retired.
BR_INST_RETIRED.FAR_BRANCH
- (Event C4H, Umask 40H) Number of far branches retired.
BR_MISP_RETIRED.ALL_BRANCHES
- (Event C5H, Umask 00H) Mispredicted branch instructions at
retirement.
BR_MISP_RETIRED.CONDITIONAL
- (Event C5H, Umask 01H) Mispredicted conditional branch instructions
retired.
BR_MISP_RETIRED.NEAR_CALL
- (Event C5H, Umask 02H) Direct and indirect mispredicted near call
instructions retired.
BR_MISP_RETIRED.ALL_BRANCH
- (Event C5H, Umask 04H) Mispredicted macro branch instructions
retired.
BR_MISP_RETIRED.NOT_TAKEN
- (Event C5H, Umask 10H) Mispredicted not taken branch instructions
retired.
BR_MISP_RETIRED.TAKEN
- (Event C5H, Umask 20H) Mispredicted taken branch instructions
retired.
FP_ASSIST.X87_OUTPUT
- (Event CAH, Umask 02H) Number of X87 assists due to output value.
FP_ASSIST.X87_INPUT
- (Event CAH, Umask 04H) Number of X87 assists due to input value.
FP_ASSIST.SIMD_OUTPUT
- (Event CAH, Umask 08H) Number of SIMD FP assists due to Output
values.
FP_ASSIST.SIMD_INPUT
- (Event CAH, Umask 10H) Number of SIMD FP assists due to input values.
FP_ASSIST.ANY
- (Event CAH, Umask 1EH) Cycles with any input/output SSE* or FP
assists.
ROB_MISC_EVENTS.LBR_INSERTS
- (Event CCH, Umask 20H) Count cases of saving new LBR records by
hardware.
MEM_TRANS_RETIRED.LOAD_LATENCY
- (Event CDH, Umask 01H) Sample loads with specified latency threshold. PMC3
only. Specify threshold in MSR 0x3F6.
MEM_TRANS_RETIRED.PRECISE_STORE
- (Event CDH, Umask 02H) Sample stores and collect precise store operation
via PEBS record. PMC3 only.
MEM_UOP_RETIRED.LOADS
- (Event D0H, Umask 01H) Qualify retired memory uops that are loads. Combine
with umask 10H, 20H, 40H, 80H.
MEM_UOP_RETIRED.STORES
- (Event D0H, Umask 02H) Qualify retired memory uops that are stores.
Combine with umask 10H, 20H, 40H, 80H.
MEM_UOP_RETIRED.STLB_MISS
- (Event D0H, Umask 10H) Qualify retired memory uops with STLB miss. Must
combine with umask 01H, 02H, to produce counts.
MEM_UOP_RETIRED.LOCK
- (Event D0H, Umask 20H) Qualify retired memory uops with lock. Must combine
with umask 01H, 02H, to produce counts.
MEM_UOP_RETIRED.SPLIT
- (Event D0H, Umask 40H) Qualify retired memory uops with line split. Must
combine with umask 01H, 02H, to produce counts.
MEM_UOP_RETIRED_ALL
- (Event D0H, Umask 80H) Qualify any retired memory uops. Must combine with
umask 01H, 02H, to produce counts.
MEM_LOAD_UOPS_RETIRED.L1_HIT
- (Event D1H, Umask 01H) Retired load uops with L1 cache hits as data
sources. Must combine with umask 01H, 02H, to produce counts.
MEM_LOAD_UOPS_RETIRED.L2_HIT
- (Event D1H, Umask 02H) Retired load uops with L2 cache hits as data
sources.
MEM_LOAD_UOPS_RETIRED.LLC_HIT
- (Event D1H, Umask 04H) Retired load uops which data sources were data hits
in LLC without snoops required.
MEM_LOAD_UOPS_RETIRED.HIT_LFB
- (Event D1H, Umask 40H) Retired load uops which data sources were load uops
missed L1 but hit FB due to preceding miss to the same cache line with
data not ready.
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
- (Event D2H, Umask 01H) Retired load uops which data sources were LLC hit
and cross-core snoop missed in on-pkg core cache.
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
- (Event D2H, Umask 02H) Retired load uops which data sources were LLC and
cross-core snoop hits in on-pkg core cache.
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
- (Event D2H, Umask 04H) Retired load uops which data sources were HitM
responses from shared LLC.
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
- (Event D2H, Umask 08H) Retired load uops which data sources were hits in
LLC without snoops required.
MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS
- (Event D4H, Umask 02H) Retired load uops with unknown information as data
source in cache serviced the load.
L2_TRANS.DEMAND_DATA_RD
- (Event F0H, Umask 01H) Demand Data Read requests that access L2
cache.
L2_TRANS.RF0
- (Event F0H, Umask 02H) RFO requests that access L2 cache.
L2_TRANS.CODE_RD
- (Event F0H, Umask 04H) L2 cache accesses when fetching instructions.
L2_TRANS.ALL_PF
- (Event F0H, Umask 08H) L2 or LLC HW prefetches that access L2 cache.
L2_TRANS.L1D_WB
- (Event F0H, Umask 10H) L1D writebacks that access L2 cache.
L2_TRANS.L2_FILL
- (Event F0H, Umask 20H) L2 fill requests that access L2 cache.
L2_TRANS.L2_WB
- (Event F0H, Umask 40H) L2 writebacks that access L2 cache.
L2_TRANS.ALL_REQUESTS
- (Event F0H, Umask 80H) Transactions accessing L2 pipe.
L2_LINES_IN.I
- (Event F1H, Umask 01H) L2 cache lines in I state filling L2. Counting does
not cover rejects.
L2_LINES_IN.S
- (Event F1H, Umask 02H) L2 cache lines in S state filling L2. Counting does
not cover rejects.
L2_LINES_IN.E
- (Event F1H, Umask 04H) L2 cache lines in E state filling L2. Counting does
not cover rejects.
L2_LINES-IN.ALL
- (Event F1H, Umask 07H) L2 cache lines filling L2. Counting does not cover
rejects.
L2_LINES_OUT.DEMAND_CLEAN
- (Event F2H, Umask 01H) Clean L2 cache lines evicted by demand.
L2_LINES_OUT.DEMAND_DIRTY
- (Event F2H, Umask 02H) Dirty L2 cache lines evicted by demand.
L2_LINES_OUT.PF_CLEAN
- (Event F2H, Umask 04H) Clean L2 cache lines evicted by L2 prefetch.
L2_LINES_OUT.PF_DIRTY
- (Event F2H, Umask 08H) Dirty L2 cache lines evicted by L2 prefetch.
L2_LINES_OUT.DIRTY_ALL
- (Event F2H, Umask 0AH) Dirty L2 cache lines filling the L2. Counting does
not cover rejects.
SQ_MISC.SPLIT_LOCK
- (Event F4H, Umask 10H) Split locks in SQ.
pmc(3),
pmc.atom(3),
pmc.core(3),
pmc.corei7(3),
pmc.corei7uc(3),
pmc.iaf(3),
pmc.ivybridge(3),
pmc.ivybridgexeon(3),
pmc.k7(3),
pmc.k8(3),
pmc.sandybridgeuc(3),
pmc.sandybridgexeon(3),
pmc.soft(3),
pmc.tsc(3),
pmc.ucf(3),
pmc.westmere(3),
pmc.westmereuc(3),
pmc_cpuinfo(3),
pmclog(3),
hwpmc(4)
The pmc library first appeared in
FreeBSD 6.0.
The Performance Counters Library (libpmc, -lpmc) library
was written by Joseph Koshy
<jkoshy@FreeBSD.org>.
The support for the Sandy Bridge microarchitecture was written by
Davide Italiano
<davide@FreeBSD.org>.
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