I2C bus system
system provides a uniform, modular and
architecture-independent system for the implementation of drivers to control
various I2C devices and to utilize different I2C controllers.
I2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed in
the early 1980's by Philips semiconductors. Its purpose was to provide an easy
way to connect a CPU to peripheral chips in a TV-set.
The BUS physically consists of 2 active wires and a ground connection. The
active wires, SDA and SCL, are both bidirectional. Where SDA is the Serial
DAta line and SCL is the Serial CLock line.
Every component hooked up to the bus has its own unique address whether it is a
CPU, LCD driver, memory, or complex function chip. Each of these chips can act
as a receiver and/or transmitter depending on its functionality. Obviously an
LCD driver is only a receiver, while a memory or I/O chip can both be
transmitter and receiver. Furthermore there may be one or more BUS MASTERs.
The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol
specification it is stated that the IC that initiates a data transfer on the
bus is considered the BUS MASTER. At that time all the others are regarded to
as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS. This
means that more than one IC capable of initiating data transfer can be
connected to it.
Some I2C device drivers are available:
||general i/o operation
||network IP interface
||I2C to SMB software bridge
The I2C protocol may be implemented by hardware or software. Software interfaces
rely on very simple hardware, usually two lines twiddled by 2 registers.
Hardware interfaces are more intelligent and receive 8-bit characters they
write to the bus according to the I2C protocol.
I2C interfaces may act on the bus as slave devices, allowing spontaneous
bidirectional communications, thanks to the multi-master capabilities of the
Some I2C interfaces are available:
||Philips PCF8584 master/slave interface
||generic bit-banging master-only driver
||parallel port specific bit-banging interface
||Brooktree848 video chipset, hardware and software master-only
The operating frequency of an I2C bus may be fixed or configurable. The bus may
be used as part of some larger standard interface, and that interface
specification may require a fixed frequency. The driver for that hardware
would not honor an attempt to configure a different speed. A general purpose
I2C bus, such as those found in many embedded systems, will often support
multiple bus frequencies.
When a system supports multiple I2C buses, a different frequency can be
configured for each bus by number, represented by the
in the variable names below. Buses can be
configured using any combination of device hints, Flattened Device Tree (FDT)
data, tunables set via
or at runtime using
When configuration is supplied using more than one method, FDT and hint data
will be overridden by a tunable, which can be overridden by
to the frequency
in Hz, on systems that use device hints to configure I2C devices. The hint is
also honored by systems that use FDT data if no frequency is configured using
Configure the I2C bus speed using the FDT standard
property of the node
describing the I2C controller hardware.
The same variable can be changed at any time with
Reset the bus using
ioctl to make the change take
manual page first appeared in
This manual page was written by Nicolas