NAME

snd_hdspe — RME HDSPe bridge device driver

SYNOPSIS

To compile this driver into the kernel, place the following lines in your kernel configuration file:

Alternatively, to load the driver as a module at boot time, place the following line in loader.conf(5):

snd_hdspe_load="YES"

DESCRIPTION

The snd_hdspe bridge driver allows the generic audio driver sound(4) to attach to RME HDSPe audio devices.

HARDWARE

The snd_hdspe driver supports the following audio devices:

• RME HDSPe AIO (optional AO4S-192 and AI4S-192 extension boards)
• RME HDSPe RayDAT

By default, each pcm(4) device corresponds to a physical port on the sound card. For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported. The effective number of ADAT channels is 8 channels at single speed (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at quad speed (128kHz-192kHz). Depending on sample rate and channel format selected, not all pcm channels can be mapped to ADAT channels and vice versa.

LOADER TUNABLES

These settings can be entered at the loader(8) prompt or in loader.conf(5).

hw.hdspe.unified_pcm

If set to 1, all physical ports are combined into one unified pcm device. When opened in multi-channel audio software, this makes all ports available at the same time, and fully synchronized. For resulting channel numbers consult the following table:

SYSCTL TUNABLES

These settings and informational values can be accessed at runtime with the sysctl(8) command. If multiple RME HDSPe sound cards are installed, each device has a separate configuration. To adjust the following sysctl identifiers for a specific sound card, insert the respective device number in place of ‘0’.

dev.hdspe.0.sample_rate

Set a fixed sample rate from 32000, 44100, 48000, up to 192000. This is usually required for digital connections (AES, S/PDIF, ADAT). The default value of 0 adjusts the sample rate according to pcm device settings.

dev.hdspe.0.period

The number of samples processed per interrupt, from 32, 64, 128, up to 4096. Setting a lower value here results in less latency, but increases system load due to frequent interrupt processing. Extreme values may cause audio gaps and glitches.

dev.hdspe.0.clock_list

Lists possible clock sources to sync with, depending on the hardware model. This includes internal and external master clocks as well as incoming digital audio signals like AES, S/PDIF and ADAT.

dev.hdspe.0.clock_preference

Select a preferred clock source from the clock list. HDSPe cards will sync to this clock source when available, but fall back to auto-sync with any other digital clock signal they receive. Set this to ‘internal’ if the HDSPe card should act as master clock.

dev.hdspe.0.clock_source

Shows the actual clock source in use (read only). This differs from what is set as clock preference when in auto-sync mode.

dev.hdspe.0.sync_status

Display the current sync status of all external clock sources. Status indications are ‘none’ for no signal at all, ‘lock’ for when a valid signal is present, and ‘sync’ for accurately synchronized signals (required for recording digital audio).

The following tunables are applicable to HDSPe AIO devices only:

dev.hdspe.0.input_level

Select the sensitivity of the analog line input. Available reference levels for the input signal are ‘LowGain’, ‘+4dBu’ and ‘-10dBV’.

dev.hdspe.0.output_level

Select the gain level of the analog line output. Available reference levels for the output signal are ‘HighGain’, ‘+4dBu’ and ‘-10dBV’.

dev.hdspe.0.phones_level

Adjust the gain level of the phones output, separately from the analog line output. Available reference levels for the output signal are ‘HighGain’, ‘+4dBu’ and ‘-10dBV’.

Where appropriate these sysctl values are modeled after official RME software on other platforms, and adopt their terminology. Consult the RME user manuals for additional information.

SEE ALSO

sound(4)

HISTORY

The snd_hdspe device driver first appeared in FreeBSD 10.0.

AUTHORS

The snd_hdspe driver was written by Ruslan Bukin <br@bsdpad.com>. Florian Walpen <dev@submerge.ch> contributed clock source settings and restructured the pcm device mapping.